The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices that have conductive lines formed by a damascene process in the back-end-of-line (BEOL).
Semiconductors are used for integrated circuits for electronic applications, including radios, televisions, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use an electron charge to store information.
A more recent development in memory devices involves spin electrics, which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. One such spin electronic device is a magnetoresistive random access memory (MRAM) device, which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is referred to as a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is stored in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment""s alignment. The stored state is read from the element by detecting the component""s resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix structure having rows and columns.
An advantage of MRAMs compared to traditional semiconductor memory devices such as DRAMs is that MRAM integrated circuits can be made smaller and provide a non-volatile memory. For example, a personal computer (PC) utilizing MRAMs would not have a long xe2x80x9cboot-upxe2x80x9d time as with conventional PCs that utilize DRAMs. MRAMs permit the ability to have a memory with more memory bits on the chip than DRAMs or flash memories. Also, an MRAM does not need to be powered up and has the capability of remembering the stored data.
A disadvantage of manufacturing MRAMs is that copper is the preferred material for conductive lines, due to the excellent conductive properties of copper compared to aluminum and other conventional metals used in semiconductor technology. A problem with using copper in the BEOL is that the copper-conductive lines must be formed using a damascene process. In a damascene process, a dielectric layer is formed, and the dielectric layer is patterned and etched to form trenches that the conductive copper lines will be formed in. When copper is used, typically a seed layer and other copper liners are used, followed by a copper fill that may be electroplated for improved fill results, for example. Copper is unable to be etched directly due to the process limitations of the copper material.
A problem in using a damascene process is that during subsequent processing steps, for example during subsequent dielectric and inter-metallic layer formation and deposition, a photoresist is often used, which must be stripped. A photoresist strip process typically involves using an oxygen plasma etch process to remove the resist. Copper oxidizes very easily, which is disadvantageous in certain semiconductor devices where the copper conductive line must have good electrical contact to subsequently deposited layers. For example, in an MRAM device, it is important for a first metallization layer conductive copper line to be electrically coupled to a magnetic stack deposited thereon.
What is needed in the art is a semiconductor device and method of fabrication thereof that prevents oxidation of copper conductive lines during processing steps involving oxygen, such as a photoresist strip.
The present invention achieves technical advantages as a device and method for fabricating conductive lines in the BEOL that prevents oxidation of the conductive lines during photoresist strip and other subsequent fabrication processes.
Disclosed is a wiring structure for semiconductor devices, comprising an inter-level dielectric (ILD) having a top surface disposed over a workpiece, conductive lines formed within the ILD, the conductive lines being recessed below the ILD top surface, and a metal cap layer disposed over the conductive lines, the metal cap layer being resistive to oxidation.
Also disclosed is an MRAM device, comprising a first ILD having a top surface disposed over a workpiece, first conductive lines formed within the first ILD, where the first conductive lines are recessed below the first ILD top surface. A first metal cap layer is disposed over the first conductive lines, the first metal cap layer being resistive to oxidation and filling the first conductive line recess. A magnetic stack is disposed over the first metal cap layer.
Further disclosed is a method of forming conductive lines in a semiconductor device, comprising depositing a first ILD having a top surface over a workpiece, patterning and etching the first ILD to form trenches, filling the trenches with a conductive material, removing portions of the conductive material from the first ILD top surface and from beneath the ILD top surface to form recesses in the conductive material below the ILD top surface, and depositing a first metal cap layer over the conductive material and the first ILD within the recess, the first metal cap layer being resistant to oxidation. The excessive metal cap layer is removed leaving only those on top of metal lines.
Also disclosed is a method of fabricating an MRAM, comprising depositing a first ILD having a top surface over a workpiece, patterning and etching the first ILD to form trenches, filling the trenches with a conductive material, removing portions of the conductive material from the first ILD top surface and from beneath the ILD top surface, wherein the conductive material is recessed below the ILD top surface, and depositing a first metal cap layer over the conductive material and the first ILD within the recess, where the first metal cap layer is resistant to oxidation. A CMP process is performed to remove the first metal cap layer everywhere but from on top of the metal. A magnetic stack is formed over the first metal cap layer, and following a magnetic stack patterning process, a second ILD having a top surface is deposited over the magnetic stack. The second ILD is patterned and etched to form trenches, the trenches are filled with a conductive material, and portions of the conductive material are removed from the second ILD top surface and from beneath the ILD top surface, wherein the conductive material is recessed below the second ILD top surface. A second metal cap layer is deposited over the conductive material and the second ILD within the recess, the second metal cap layer being resistant to oxidation.
Advantages of the invention include providing a structure and method of fabrication of conductive lines in the BEOL that prevent oxidation of conductive lines and enable electrical contact to subsequently deposited layers in the device. The conductive lines surface smoothness requirements may be relaxed in accordance with the present invention. A metal cap is used to prevent the conductive lines from oxidation during subsequent processing steps such as plasma photoresist stripping and dielectric materials deposition, eliminating or reducing the need for the use of hard masks, which is generally required to RIE a material that is directly on top of Cu, to prevent the resist stripping process while exposing Cu. Because the use of hard masks is eliminated or reduced, the number of processing steps is reduced, resulting in reduced costs and increased throughput. The metal cap may be used for multi-level lithography that has conductive lines exposed during photoresist stripping, such as in MRAM cross-point cell manufacturing, for example.